The current invention is in the field of voltage sense measurement (VSM) circuitry.
Measuring electric current (“current”) accurately is an important use of parametric testers, in particular those used for semiconductor device characterization. When high-quality Voltage Sources Measurement Units (VSMUs) are considered for use with a device-under-test (DUT), a commonly used current measurement methodology is to sense the resulting voltage drop across a precision resistor (Rnet) connected in series with the “high” end of the DUT. An example of this is disclosed in U.S. Pat. No. 7,098,648. This methodology, while simple and topologically convenient, has potential disadvantages in that the common-mode voltage across Rnet varies with output (DUT) voltage, leading to a variable offset error.
Offset errors can be significant. For example, a high quality differential amplifier may have common mode gain of 1/20,000, meaning that at output voltage (Vout) of 10 V, the offset voltage increases by 10/20,000 V, or 500 μV, relative to the offset at Vout=0 V. If the measured voltage drop across Rnet is 10 mV only (low current range, for example), the resulting relative error is 5%—which can be unacceptably high for such systems. Furthermore, for example, if Vout is 100 V, a similar current will be measured with an error of 50%.
The invention addresses this issue for a two-terminal device, primarily when the DUT is placed in close proximity to the force lines. Furthermore, the solution has additional benefits compared to conventional VSM circuitry.